/*
 *  Copyright 2000 by Texas Instruments Incorporated.
 *  All rights reserved. Property of Texas Instruments Incorporated.
 *  Restricted rights to use, duplicate or disclose this code are
 *  granted through contract.
 *  U.S. Patent Nos. 5,283,900  5,392,448
 */
/* "@(#) DSP/BIOS 4.00 09-15-00 (barracuda-e16)" */
/*
 *  ======== dss_evm62.c ========
 */

/* McBSP 0 Memory Mapped Registers */
#define DRR  (*(volatile unsigned int *)0x018c0000) /* Data Receive Reg */
#define DXR  (*(volatile unsigned int *)0x018c0004) /* Data Transmit Reg */
#define SPCR (*(volatile unsigned int *)0x018c0008) /* Serial Port Cont Reg */
#define RCR  (*(volatile unsigned int *)0x018c000c) /* Receive Control Reg */
#define XCR  (*(volatile unsigned int *)0x018c0010) /* Transmit Control Reg */
#define MCR  (*(volatile unsigned int *)0x018c0018) /* Multichannel Reg */
#define PCR  (*(volatile unsigned int *)0x018c0024) /* Pin Control Reg */

/* CPLD (Complex Programmable Logic Device) Memory Mapped Register */
#define CPLD (*(volatile unsigned int *)0x01780000)

/* Codec Memory Mapped Registers */
#define IAR  (*(volatile unsigned int *)0x01720000) /* Index Address Reg */
#define IDR  (*(volatile unsigned int *)0x01720004) /* Indexed Data Reg */
#define SR   (*(volatile unsigned int *)0x01720008) /* Status Reg */
#define PIO  (*(volatile unsigned int *)0x0172000c) /* PIO Data Reg */

/* Codec Indirect Mapped Registers */
#define DAC_LEFT_CNTL   0x06  /* I6  - Left DAC Output Control */
#define DAC_RIGHT_CNTL  0x07  /* I7  - Right DAC Output Control */
#define FS_PDF_CNTL     0x48  /* I8  - FS & Playback Data Control (MCE set) */
#define PIO_CNTL        0x49  /* I9  - Interface Control (MCE set) */
#define MODE_CNTL       0x0c  /* I12 - Mode and ID Control */
#define SP_CNTL         0x50  /* I16 - Alternate Feature enable 1 (MCE set) */
#define LINE_LEFT_CNTL  0x12  /* I18 - Left Line Input Control */
#define LINE_RIGHT_CNTL 0x13  /* I19 - Right Line Input Control */
#define CDF_CNTL        0x5c  /* I28 - Capture Data Format (MCE set)*/




/* Codec Commands */
#define DAC_UNMUTE    0x00  /* Unmute DAC-to-mixer */
#define MODE2_ENABLE  0x40  /* Enable MODE 2 */
#define INIT_DONE     0x80  /* Initialization bit */
#define SP_32_ENABLE  0x0a  /* Serial Port (32 bits) */
#define CDF_S_L16     0x50  /* CDF; Stereo, linear, 16-bit */
#define FS8_S_L16     0x50  /* FS: 8kHz, PDF; Stereo, linear, 16-bit */
#define FS48_S_L16    0x5c  /* FS: 48kHz, PDF; Stereo, linear, 16-bit */
#define PIO_ENABLE    0xc3  /* Enable PIO (capture and playback) */
#define MCE_RESET     0xbf  /* Reset Mode Control Bit (MCE) */

/* CPLD Commands */
#define CODEC_DISABLE  0xf8
#define CODEC_ENABLE   0x04


/* McBSP 0 commands */
#define SPCR_DISABLE   0x00        /* Disable serial port */
#define SPCR_STANDBY   0x00200020  /* Wait for frame synch, enable RX int */
#define SPCR_ENABLE    0x00010001  /* enable serial port */
#define PCR_SET        0x00        /* external RX/TX clock and frame synch */
#define CR_32_SET      0x000000a0  /* 32 bit word, 1 w/frame, single phase */
#define MCR_SET        0x00        /* enable TX and RX channels */
#define MCSP_RXINT_BIT 0x0800      /* assume serial RX interrupt on INT 11 */


/* Macros */
#define SETBITMASKCODEC(i,n) IAR=(i); IDR|=(n);
#define SETREGCODEC(i,n) IAR=(i); IDR=(n);


static void enableCodec(void);  /* Configure Codec */
static void enableMcBSP0(void); /* Configure McBSP 0 */

extern cregister volatile unsigned int IFR;
extern cregister volatile unsigned int ICR;
extern cregister volatile unsigned int IER;    



/*
 * ======== DSS_init ========
 */
void DSS_init(void)
{

    
    /* Configure codec */
    enableCodec();

    /* Configure McBSP 0 */
    enableMcBSP0();

    /* Unmute left and right DAC-to-mixer */
    SETREGCODEC(DAC_LEFT_CNTL, DAC_UNMUTE);
    SETREGCODEC(DAC_RIGHT_CNTL, DAC_UNMUTE);

    
}




/*
 * ======== enableCodec ========
 */
static void enableCodec(void)
{

    /* Reset and enable codec */
    CPLD &= CODEC_DISABLE;
    CPLD |= CODEC_ENABLE;

    /* wait for codec to finish initialization */
    while(IAR & INIT_DONE);
  
    /* Enable mode 2 */
    SETBITMASKCODEC(MODE_CNTL, MODE2_ENABLE);

    /* Set codec Serial port format */
    SETREGCODEC(SP_CNTL, SP_32_ENABLE);

    /* Set capture format */
    SETREGCODEC(CDF_CNTL, CDF_S_L16);

    /* Set playback format and sampling rate */
    SETREGCODEC(FS_PDF_CNTL, FS48_S_L16);

    /* Enable bits in PIO (programmed I/O) */
    SETREGCODEC(PIO_CNTL, PIO_ENABLE);

    /* Reset Mode Control Bit (MCE) */
    IAR &= MCE_RESET;


}


/*
 * ======== enableMcBSP0 ========
 */
static void enableMcBSP0(void)
{


    /* Disable serial port */
    SPCR = SPCR_DISABLE;

    /* Configure pin control register */
    PCR = PCR_SET;
    
    /* Configure receive control register */
    RCR = CR_32_SET;
    
    /* Configure transmit control register */
    XCR = CR_32_SET;

    /* Enable transmit and receive channels */
    MCR = MCR_SET;

    /* Put serial port in 'standby' and wait for frame synch */
    SPCR = SPCR_STANDBY;

    while(!(IFR & MCSP_RXINT_BIT));

    /* Clear the frame synch interrupt */
    ICR = MCSP_RXINT_BIT;

    /* Enable serial port */
    SPCR = SPCR_ENABLE;

    /* Enable INT 11 */
    IER |= MCSP_RXINT_BIT;
}