Faramatic™: Capacitor Network Synthesizer

Faramatic™ Synthesizer & Hysteresis Resolver

Normal Synthesis

Capacitors (n): 4

Engine Architecture:

Base Capacitor Progression (C₁ … C_n): Quick Select:

Target Objective:

Singularity Stress Test:

Pareto States --

Game Fit --%

Fit NRMSE --%

BOM Cost $0.00

Span ΔC --

Min Step ΔC_min --

Max Gap ΔC_max --

Package Range --

Base Capacitors & Required Packages: Seed Mode

Boundary Ranges & Switch Fabric

Log₁₀ Bounds (pF)

C_min: 100 pF

10²

C_max: 100 nF

10⁵

Capacitor Class:

Tolerance:

Base ESR (mΩ):

Switch Fabric Architecture:

Switches:--

R_on:-- Ω

C_off:-- pF

State Sequence Scrubber & Switching Engine

State 1 / 1

Switch Sequentiality: 0% (Parallel)

Switch Toggles:ΔS = 0

Glitch Energy:-- nJ

T_settle:-- μs

Active Circuit Schematic (Crisp Single-Pixel Canvas): --

Capacitors: 42×24px [Index Only]

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Pareto Selection Justification:

Canonical optimal selection: Lowest equivalent series resistance ESR_eq and fewest toggled switches across equivalent capacitance paths.

Y-Scale:

• Dark Line: Synthesized Pareto States • Shaded Area: Precision Envelope [±P] • Stepped Red Line: Minimum Required SMD Footprint

Active Op-Amp Filter / Miller Integrator Parameters:

R_ref: Ω GBW: MHz

Dielectric Physics, Volumetric Footprint Scaling & Pareto Degeneracy

Faramatic™ Physical Theory

Dielectric Volumetric Limit Law

$$\text{Vol} \ge \frac{C \cdot V_{\text{rated}}^2}{\varepsilon_0 \varepsilon_r E_{\text{breakdown}}^2}$$

Why Capacitors Must Scale in Size: Unlike thin-film resistors where sheet resistivity $\rho/t$ and laser trimming allow any value from $1\,\Omega$ to $10\,\text{M}\Omega$ in an invariant 0603 footprint, electrostatic energy storage requires physical dielectric volume. High capacitance forces footprint jumps: 0402 ($\le 10\,\text{nF}$) → 0603 ($\le 220\,\text{nF}$) → 0805 ($\le 2.2\,\mu\text{F}$) → 1206 ($\le 10\,\mu\text{F}$) → 1210 / Tantalum ($> 10\,\mu\text{F}$).

Pareto State Count Disparity

$$\frac{\Delta C}{C_{\text{large}}} = \frac{C_{\text{small}}}{C_{\text{large}}} < \varepsilon_{\text{cluster}}$$

Extreme Decade Masking: When synthesized values span $\ge 3$ decades, combining extreme parts ($C_{\text{large}} \parallel C_{\text{small}}$) creates relative shifts smaller than the Pareto clustering tolerance ($\varepsilon < 0.15\%$). The Pareto optimizer collapses these topologically distinct formulas into a single cluster. Faramatic employs an adaptive threshold $\varepsilon_{\text{cluster}} = \min(0.0015, P/5)$ to preserve high-precision states.

Equivalent Series Resistance (ESR)

$$ESR_{\text{series}} = \sum_k ESR_k, \quad \frac{1}{ESR_{\text{parallel}}} = \sum_k \frac{1}{ESR_k}$$

Capacitor parasitics track as equivalent series resistance ($ESR$) and switch $R_{\text{on}}$. Parallel combinations compound capacitance while dividing $ESR$, yielding high $Q$-factor states. In filtering, $ESR$ and interconnect parasitics determine the ultimate high-frequency stopband floor.

Lockstep Rank-1 Singularity

$$\mu([C_0, C_0]) = 0 \implies n = 1, \quad C_{\text{min}} \equiv C_{\text{max}}$$

When $C_{\text{min}} = C_{\text{max}}$, the target interval has zero measure, collapsing degrees of freedom to $n = 1$. The state machine enters lockstep array mode: both boundaries travel together. Dragging $n > 1$ or clicking the decouple badge immediately restores the prior multi-capacitor state from hysteresis memory.