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Ohmatic™: E24/E96 Resistor & Divider Network Synthesizer

L. Van Warren, PhD • Version-II Master © 2026 • Async Worker DP + Y(jω) RLC Engine Worker DP: Ready (n≤8)

Press [E] to toggle E24/E96 Quantization • Complex Nodal $\mathbf{Y}(j\omega)$ with Package ESL • Exact Sub-Tree BBM/MBB Glitch Bounds • Johnson-Nyquist $e_n$ Noise • SPICE & KiCad Netlists

Ohmatic™ Synthesizer & E-Series Quantizer

Normal Synthesis
4
EIA Decade Quantization (Shortcut E): E96 (1%)
Quick Select:
Pareto States --
Game Fit --%
Fit NRMSE --%
BOM Cost $0.00
Span ΔR --
Min Step ΔRmin --
Max Gap ΔRmax --
Span Ratio SR --
Quantized Base Resistors (1..n, TCR Adjusted): Seed Mode

Bounds, Parasitic RLC, Thermal Derating & Switch Fabric

P_derate: 100% (25°C)
10 kΩ
104
1.0 MΩ
106
25°C
+0.00%
Switches:--
R_on (eff):-- Ω
C_off / C_gnd:-- pF

Fast E24/E96 Target Solver (<2ms) & Thermal Derating Envelope

0.12 ms
47.0 kΩ
70°C–155°C Derating & Error HUD: #res-canvas

State Sequence Scrubber, Exact BBM/MBB Bounds & Thermal Noise

State 1 / 1
0% (Parallel)
Toggles:ΔS = 0
BBM Peak:-- Ω
MBB Dip:-- Ω
Noise en:-- nV/√Hz
Glitch E:-- nJ
T_settle:-- μs
Active Circuit Schematic (Crisp Single-Pixel Canvas): --
Resistors: 42×24px [Index Only]
✓
Pareto Selection, Nodal RLC Admittance & Johnson Noise Summary:

Canonical optimal selection: Lowest parasitic capacitance C_eq and fewest toggled switches across equivalent resistance paths.

Y-Scale:
• Dark Line: Synthesized Pareto States (with R_on & TCR) • Shaded Area: Precision + Thermal Envelope • Dashed Line: Ideal Objective
Inverting Op-Amp $\mathbf{Y}(j\omega)$ RLC Feedback Parameters:

Mathematical Models, Nodal RLC Admittance $\mathbf{Y}(j\omega)$, Johnson-Nyquist Noise & Sub-Tree Glitch Bounds

Ohmatic™ Synthesis Theory

Singularity Hysteresis & Lockstep

$$\Delta R_{\text{span}} = R_{\text{max}} - R_{\text{min}}, \quad \mu([R_0, R_0]) = 0$$

Lockstep Coupling Theorem: When $n = 1$, the resistor array synthesizes a single degenerate state and $R_{\text{min}}, R_{\text{max}}$ travel in lockstep. Reciprocally, when $R_{\text{min}} = R_{\text{max}}$, network degrees of freedom collapse to $n = 1$ while preserving $n_{\text{prior}} \ge 2$ in hysteresis memory.

$$R_k(T_{\text{amb}}) = R_{k,25^\circ\text{C}}\left[1 + \alpha_{\text{TCR}}\cdot 10^{-6}(T_{\text{amb}} - 25)\right]$$

Async WebWorker DP & E24/E96

$$M_{m}^{(d)} = 10^{d} \cdot \text{round}\!\left(10^{\frac{m}{N_{\text{ser}}}}\right), \quad N_{\text{ser}} \in \{12, 24, 96\}$$

Cograph synthesis partitions bitmasks $m \in [1, 2^n - 1]$ for $n \le 8$ inside a non-blocking WebWorker, pruning dominated $(\text{mask}, R_{\text{eq}}, C_{\text{eq}})$ subtrees before Pareto selection:

$$\arg\min \Big[ C_{\text{eq}}(\mathcal{T}) \Big] \to \arg\min \Big[ \Delta S(\mathcal{T}) \Big] \to \arg\max \Big[ I_{\text{max}}(\mathcal{T}) \Big]$$

Nodal RLC Admittance $\mathbf{Y}(j\omega)$ & Noise

$$y_{\text{RLC}}(j\omega) = \frac{R_{\text{eff}}}{R_{\text{eff}}^2 + (\omega L_s)^2} + j\!\left(\omega C_p - \frac{\omega L_s}{R_{\text{eff}}^2 + (\omega L_s)^2}\right)$$

Each branch incorporates switch $R_{\text{on}}$, package series inductance $L_s$ ($\text{ESL}$), and shunt $C_p$, while internal Cograph junctions inject $j\omega C_{\text{sw-gnd}}$. Thermal voltage noise density follows Johnson-Nyquist statistics:

$$e_n = \sqrt{4 k_B (T_{\text{amb}} + 273.15) R_{\text{eq}}} \quad [\text{nV}/\sqrt{\text{Hz}}]$$

Exact Sub-Tree BBM / MBB & Derating

$$R_{\text{MBB,dip}} = R(S^{(k-1)}) \parallel R(S^{(k)}), \quad R_{\text{BBM,peak}} = R_{\mathcal{T}}\!\left(S^{(k-1)} \cap S^{(k)}\right)$$

Make-Before-Break bridges states in parallel causing a low-Z dip, whereas Break-Before-Make recursively evaluates the Cograph sub-tree with non-surviving leaves set to $R_{\text{off}} = 100\,\text{M}\Omega$. Above $70^\circ\text{C}$, power derates linearly to $0\,\text{W}$ at $155^\circ\text{C}$:

$$P_{\text{max}}(T_{\text{amb}}) = P_{70^\circ\text{C}} \cdot \max\!\left(0, \min\!\left(1, \frac{155 - T_{\text{amb}}}{85}\right)\right)$$